As the integration level of semiconductor devices, such as DRAMs, is increased, a capacitor based cell area therein may be decreased. Moreover, it may be difficult to provide the needed capacitance for the capacitor even if a dielectric layer formed of oxide layer/nitride layer (SiO2/Si3N4) is thinned. Accordingly, various research has been conducted for enlarging a surface area of a capacitor to secure a required capacitance. For example, an increased height capacitor can be formed in a semiconductor substrate, however, this approach may result in a surface of an electrode of the capacitor being unevenly formed. In a highly integrated DRAM device of 1 giga bit (Gb) and higher, the dielectric layer of oxide layer/nitride layer that has a low dielectric constant may be difficult to further thin to increase the capacitance. Moreover, if the capacitor is formed by a complicated process of enlarging the surface area of the capacitor, the fabricating process may become considerably more complex, thereby possibly degrading yield and increasing fabricating cost.
One approach used in view of the problems discussed above involves the use of a high dielectric material layer with a high dielectric constant. The high dielectric material layer can include Ba1-xSrxTiO3 (BST) layer, etc. The BST layer may be attractive because of relatively high dielectric constant, but may present significant problems associated with reproducibility of compositions of chemical elements such as Ba, Sr and Ti.